1. Field of the Invention
Generally, the present disclosure relates to integrated circuits and methods for the formation thereof, and, in particular, to integrated circuits including field effect transistors that are provided over backgate regions and methods for the formation thereof.
2. Description of the Related Art
Integrated circuits include a large number of circuit elements which include, in particular, field effect transistors. In a field effect transistor, a gate electrode is provided that may be separated from a channel region by a gate insulation layer providing an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are formed, which are doped differently than the channel region.
Integrated circuits including field effect transistors may be formed in accordance with the semiconductor-on-insulator (SOI) technology, wherein the source, channel and drain regions of the transistors are formed in a thin semiconductor layer that is separated from a support substrate, which may be a semiconductor substrate, for example a silicon wafer or die, by an electrically insulating layer, which may be a silicon dioxide layer. SOI technology may have some advantages associated therewith, which include a reduced power consumption of an SOI integrated circuit compared to a bulk semiconductor integrated circuit having the same performance.
Additionally, SOI technology may allow doped backgate regions in the support substrate below the electrically insulating layer that separates the support substrate from the semiconductor material of the source, channel and drain regions of the transistors. The type of doping and the dopant concentration in a backgate region provided below a transistor can have an influence on the threshold voltage of the transistor that needs to be applied to the gate electrode of the transistor for switching the transistor between an on-state wherein the transistor has a relatively high electrical conductivity and an off-state. Additionally, the threshold voltage of the transistor can be influenced by applying a bias voltage to the backgate region.
The threshold voltage of a field effect transistor may be related to a leakage current that flows through the transistor in the off-state. Typically, a lower threshold voltage is associated with an increased leakage current, and vice versa. Lowering the threshold voltage of the field effect transistors in an integrated circuit may help to increase the speed of operation of logic gates wherein the transistors are provided, whereas a reduction of the leakage current may help to reduce power consumption.
Grenouillet et al., “UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20 nm node and below,” IEEE Electron Devices Meeting (IEDM), pages 3.6.1 to 3.6.4, 2012, discloses providing P-doped well regions in the support substrate of an SOI integrated circuit. The P-doped well regions are separated from each other by deep trenches. Above each of the P-doped well regions, either N-channel field effect transistors or P-channel field effect transistors are provided, wherein the electrically insulating layer of the SOI structure is provided between the transistors and the P-doped wells. Below the P-doped wells, an N-doped deep well is provided. Additionally, in the P-doped wells, shallow N-doped backgate regions may be provided. Contacts are provided, which allow applying voltages to the deep N-doped well, the P-doped wells and the shallow N-doped backgate regions.
However, the solution described by Grenouillet et. al. has some issues associated therewith. Due to the contacts provided to the P-doped wells and to the shallow N-doped backgate regions in the wells, a large number of contacts needs to be provided, which can significantly increase the area required by the integrated circuit and can reduce the transistor density of the integrated circuit.
Furthermore, the shallow N-doped backgate regions are formed by means of ion implantation, wherein a counterdoping scheme is used, i.e., the shallow N-doped backgate regions are initially doped with the P-doping of the P-doped wells. Accordingly, a relatively high density of N-type dopants may be required for reversing the polarity of the shallow N-doped backgate regions. Accordingly, the implants for forming the shallow N-doped backgate regions may require relatively high doses, so that the total number of ions passing through the surface and the electrically insulating layer of the SOI structure may be about twice that which would be required to just dope the shallow N-doped backgate regions. Accordingly, a number of damages caused by the ions may be increased.
Furthermore, the design of an integrated circuit as described by Grenouillet et. al. may require additional routing for providing electrical connections to contacts to the shallow N-doped backgate regions and the P-doped wells.
The present disclosure provides semiconductor structures and methods that may help to overcome or at least reduce some or all of the above-mentioned issues of the prior art.